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STALL_MASTER Operation
When STALL_MASTER is asserted, the likelihood that the PCI arbiter will remove the PCI bus grant signal during
the DMA startup sequence is greatly increased. The bus is idle while the core delays asserting FRAMEN, and the
arbiter may remove the bus grant if a higher priority device requests the bus. This will cause the core to terminate the
DMA cycle. DP_DONE will be asserted, as shown in Figure 6-48 .
When GNTN is removed, the core aborts the current DMA cycle. The core will restart the cycle when the bus is
regranted. At that time, it will reread the data from the backend. The core will not reread the data if FIFO recovery
mode is enabled in the core. The core will continue to request the bus until it manages to start a cycle and FRAMEN is
asserted.
In some systems, this could prevent the core from being given sufficient bus access, preventing data from being
transferred at the expected rate.
STALL_MASTER must not be used to inject more than a 16-clock-cycle delay from DP_START to FRAMEN
assertion. Doing so would violate the PCI specification. The core should assert FRAMEN within 16 clock cycles of
GNTN assertion.
cycle 90 91 A0 A1 A2 A3 A4 A5 A6 A7 A0 A1 A2 A3 A4 A5 A6 A7 A0 A1 A2 A3 0 1 2 3 4 5 6 7
clk
framen
cben[3:0]
ad[31:0]
7
ADDR
7
ADDR
7
ADDR
0
0
1 2 3
Z
par
devseln
irdyn
trdyn
reqn
gntn
stall_master
mast_active
dp_start
dp_done
bar_select[2:0]
0
7
0
7
0
rd_cyc
rd_stb_out
rd_stb_in
mem_data_in[31:0]
0 1 2 3 4 5
mem_add[11:0]
000
004 008 00C 010 014
rd_sync
Figure 6-48 · STALL_MASTER Assertion and Cycle Aborted due to Loss of GNTN
v4.0
97
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